1. Field of the Invention
The present invention relates to a semiconductor device and a method of supplying internal power to the semiconductor device.
In particular, the present invention relates to a semiconductor device having a configuration in which an externally supplied power voltage is stepped down to an internal power voltage, and an internal power is supplied to each circuit provided in the semiconductor device.
2. Description of Related Art
As an example of semiconductor devices, there are known semiconductor memories using DRAM memory cells. To enhance the integration degree of each semiconductor memory, peripheral transistors constituting memory devices and peripheral circuits have been miniaturized. Along with a further miniaturization of the memory devices and peripheral transistors, the voltage that can be applied to these devices is limited to a low voltage so that high operation reliability is secured. On the other hand, it is important for each semiconductor memory to maintain compatibility as a product. Accordingly, the semiconductor memory needs to operate with accuracy, even if a power supply voltage is externally supplied in a conventional manner.
In specifications in which a voltage of 1.8 V is supplied as an external power supply voltage, for example, when it is assumed that a power supply voltage of up to 1.5 V can be applied to a device in terms of reliability, it is necessary to drop the external power supply voltage of 1.8 V to 1.5 V by using a step-down circuit provided in the semiconductor memory, and to supply the voltage thus obtained to memory devices and peripheral transistors as an internal power supply voltage.
The voltage to be supplied to the peripheral circuits is limited to a small voltage by the step-down circuit as described above, thereby obtaining an effect of reducing the amplitude of an operating voltage of each peripheral circuit and reducing the consumption current of the semiconductor memory, aside from the effect of securing high reliability.
As described above, it is necessary for the semiconductor device to generate an internal power supply voltage that can be used in internal circuits by converting the externally supplied power supply voltage.
When the step-down circuit is incorporated into the semiconductor device, a plurality of step-down circuits is dispersed on a chip.
Because the memory capacity of the semiconductor memory increases, resulting in an increase in chip size, for example; and the consumption current of peripheral circuits has been increased along with a high-speed operation.
FIG. 11 is a block diagram showing the configuration of a semiconductor memory 1 of the related art using DRAM memory cells.
The semiconductor memory 1 includes peripheral circuits 10 and a memory core circuit 20. The semiconductor memory 1 is supplied with input/output data signals DQ0 and DQ1 to DQ31, control signals CE and WE to CLK, address signals A0 and A1 to An, a power supply voltage VDD, and a ground voltage GND from the outside of the semiconductor memory through bonding pads.
As the peripheral circuits 10, there are provided a data control circuit 11, a command control circuit 12, an address control circuit 13, and a data control circuit 14.
Although not shown in FIG. 11, a power supply control circuit, a test circuit, and the like may be provided.
The input/output data signals DQ0 to DQ15 are input to/output from the data control circuit 11, and the input/output data signals DQ16 to DQ31 are input to/output from the data control circuit 104.
The memory core circuit 20 includes a DRAM memory cell array 25, an array data-related circuit 21, an array control-related circuit 22, an array address-related circuit 23, and an array data-related circuit 24. The array data-related circuit 21, the array control-related circuit 22, the array address-related circuit 23, and the array data-related circuit 24 are used for controlling the DRAM memory cell array 25 in accordance with data, commands, and addresses received from the peripheral circuits 10.
The input/output data signals DQ0 to DQ15 are input to/output from the array data-related circuit 21, and the input/output data signals DQ16 to DQ31 are input to/output from the array data-related circuit 24.
FIG. 12 is a block diagram showing a circuit configuration for supplying voltage to the peripheral circuits 10.
The power supply voltage VDD passes through a step-down circuit group 16 and becomes an internal power supply voltage VDL. Then, the internal power supply voltage VDL is supplied to the data control circuit 11, the command control circuit 12, the address control circuit 13, and the data control circuit 14, and is further supplied to a power-on reset circuit 15 for initializing the peripheral circuits after power-on.
The step-down circuit group 16 includes step-down circuits 16V1 to 16V8 which are dispersed.
The plurality of step-down circuits 16V1 to 16V8 is dispersed as described above, which makes it possible to design the circuit such that a drop of an internal voltage generated by an operating current of the peripheral circuits during the operation of the semiconductor memory is limited to a predetermined level to secure the operation.
In this case, the internal power supply voltages VDL, which are supplied to the data control circuit 11, the command control circuit 12, the address control circuit 13, the data control circuit 14, and the power-on reset circuit 15, are respectively represented by VDL1, VDL2, VDL3, VDL4, and VDLP.
FIG. 13 is a circuit diagram showing the power-on reset circuit 15.
FIG. 14 is a voltage waveform chart illustrating the operation of the power-on reset circuit 15.
The power-on reset circuit 15 includes resistor elements R1, R2, R3, and R4, p-type MOSFETs MP1 and MP2, and n-type MOSFETs MN1 and MN2.
As shown in FIG. 13, it is assumed herein that a potential at a node between the resistor elements R1 and R2 is represented by Vr1; a potential at a node between the p-type MOSFET MP1 and the resistor element R3 is represented by Vr2; and a potential at a node between the resistor element R4 and the n-type MOSFET MN1 is represented by Vr3.
It is also assumed that R1=R2; a threshold voltage of each of the p-type MOSFETs MP1 and MP2 is expressed by Vtp=−0.4 V; and a threshold voltage of each of the n-type MOSFETs MN1 and MN2 is expressed by Vtn=0.4 V.
The operation of the power-on reset circuit 15 will be described with reference to FIG. 14.
Each node of the power-on reset circuit 15 is set to a ground level (0 V) before the internal power supply voltage VDLP rises. Then, the internal power supply voltage VDL starts to rise. In this case, the potential Vr1 is determined by a value which is obtained by dividing the internal power supply voltage VDLP using the resistor elements R1 and R2.VR1=VDLP×R2/(R1+R2)
As apparent from the above formula, the potential Vr1 rises with the internal power supply voltage VDLP at a ratio represented by the above formula.
In the process in which the internal power supply voltage VDLP rises, a potential difference (Vr1-VDLP) between the gate and source of the p-type MOSFET MP1 does not exceed the threshold voltage Vtp in a region where the internal power supply voltage VDLP is equal to or higher than 0 V and lower than 0.8 V (in a time period prior to a time TRST). Accordingly, the p-type MOSFET MP1 is in a non-conductive state.
In this case, the potential Vr2 is fixed at 0 V, and thus the n-type MOSFET MN1 is also in a non-conductive state.
When the Vr3 is pulled up to the internal power supply voltage VDL by the resistor element R4, the n-type MOSFET MN2 is turned on and an output RST is maintained at 0 V.
When the internal power supply voltage VDLP exceeds 0.8 V (in a time period after the time TRST), the potential difference (Vr1-VDLP) between the gate and source of the p-type MOSFET MP1 exceeds the threshold voltage Vtp, and the p-type MOSFET MP1 is rendered conductive. Then, as the potential Vr2 rises, the MN1 is rendered conductive. When the potential Vr3 is pulled down, the p-type MOSFET MP2 is turned on and the output RST changes to high level.
As described above, in the power-on reset circuit 15 shown in FIG. 13, the output RST becomes low level in the region in which the internal power supply voltage VDL is equal to or higher than 0 V and lower than 0.8 V, and the output RST becomes high level when the internal power supply voltage VDLP exceeds 0.8 V.
An inversion level (0.8 V in the above example) of the power-on reset circuit 15 is generally set by giving a margin to the level of the internal power supply voltage VDL at which the circuits (e.g., the data control circuits 11 and 14, the command control circuit 12, and the address control circuit 13) receiving the initialization signal RST can execute an initialization operation normally.
For example, if the data control circuits 11 and 14, the command control circuit 12, and the address control circuit 13 can be normally initialized with the internal power supply voltage VDL of 0.6 V or higher, the inversion level of the power-on reset circuit 15 is generally set to about 0.8 V, as in the above example.
On the other hand, when the inversion level of the power-on reset circuit 15 is raised, a sufficient margin for the initialization is secured. However, during the normal circuit operation, a malfunction may frequency occur in which the power-on reset circuit 15 responds to a small voltage drop of the internal power supply voltage VDL and issues the initialization operation again. Thus, the inversion level of the power-on reset circuit 15 cannot be easily set to high level.
FIG. 15 is a diagram showing the circuit configuration of the step-down circuits 16V1 to 16V8 of the related art.
Each of the step-down circuits 16V1 to 16V8 includes a differential circuit section 16A, a current control section 16B, and a voltage supply section 16C. The differential circuit section 16A includes p-type MOSFETs MP12 and M1213 and n-type MOSFETs MN12 and MN13. The current control section 16B includes a p-type MOSFET MP11, a resistor R11, and n-type MOSFETs MN11 and MN14. The voltage supply section 16C includes a p-type MOSFET MP14 and resistors R12 and R13. Further, a reference voltage VREF for setting the level of the output voltage VDL is input to the gate of the n-type MOSFET MN12.
Note that a potential at a node between the resistors R12 and R13 is represented by VMON.
The levels of the internal power supply voltages VDL generated by the step-down circuits 16V1 to 16V8 are determined by the reference voltage VREF serving as an input of the differential circuit section 16A, and the divided voltage VMON which is determined by the resistors R12 and R13.
In this case, the level of the voltage VMON is expressed by the following formula.VMON=VDL×R13/(R12+R13)
When a comparison ratio of the differential circuit section 16A is 1:1, a stabilization point is expressed by VREF=VMON, and the following formula is obtained.VREF=VMON=VDL×R13/(R12+R13)From this formula, the following formula is obtained.VDL=VREF×(R12+R13)/R13 
In the case where the internal power supply voltage VDL is set to 1.5 V when the external power supply voltage VDD is 1.8 V, it is apparent from the above formula that VREF=0.75V, R12=R13, for example, are satisfied.
FIG. 16 is a voltage waveform chart illustrating the operation of the step-down circuits 16V1 to 16V8.
The operation of the step-down circuits 16V1 to 16V8 will be described with reference to FIG. 16. When the reference voltage VREF is set to 0.75 V after power-on of the external power supply VDD, the step-down circuits 16V1 to 16V8 raise the level of the internal power supply voltage VDL. As the internal power supply voltage VDL rises, the level of the voltage VMON also rises. Then, when the internal power supply voltage VDL rises up to 1.5 V, the voltage VMON becomes 0.75 V and VREF=VMON is satisfied. Accordingly, the internal power supply voltage VDL is controlled at 1.5 V.
As shown in FIG. 12, the internal power supply voltages VDL1, VDL2, VDL3, VDL4, and VDLP, which are respectively supplied to the functional circuits 11 to 15, are set to the same voltage level in terms of DC. However, the voltage levels of the internal power supply voltages in terms of AC during the power-on process or circuit operation vary due to the effects of the consumption current, parasitic capacitance, and power supply wiring resistance of their functional circuits.
Reference is now made to FIG. 17 which is a graph showing the effects of the parasitic capacitance on the rise of the internal power supply voltage VDL during the power-on process.
In FIG. 17, the horizontal axis represents time and the vertical axis represents the voltage level of the internal power supply voltage VDL.
It is assumed herein that each of the step-down circuits 16V1 to 16V8 has a small power supply capability corresponding to the power-on process.
In FIG. 17, L01 represents a voltage transition when a circuit having a parasitic capacitance CL of 2000 pF is started using a constant current of 1 mA; L02 represents a voltage transition when a circuit having a parasitic capacitance CL of 3000 pF is started; and L03 represents a voltage transition when a circuit having a parasitic capacitance CL of 5000 pF is started using a constant current of 1 mA.
As shown in FIG. 17, when the parasitic capacitance is small (e.g., CL=2000 pF or CL=3000 pF), the voltages L01 and L02 rise relatively quickly along with the internal power supply voltage VDL. Meanwhile, when the parasitic capacitance is large (e.g., CL=5000 pF), the voltage L03 rises with a significant delay from the internal power supply voltage VDL.
It is assumed in FIG. 12 that the parasitic capacitance of the data control circuit 11 supplied with the internal power supply voltage VDL1 is 2000 pF; the parasitic capacitance of the command control circuit 12 supplied with the internal power supply voltage VDL2 is 5000 pF; the parasitic capacitance of the address control circuit 13 supplied with the internal power supply voltage VDL3 is 3000 pF; and the combined parasitic capacitance of the data control circuit 14 and the power-on reset circuit 15, which are respectively supplied with the internal power supply voltages VDL4 and VDLP, is 2000 pF. It is also assumed that each parasitic capacitance is raised using a constant current of 1 mA for ease of explanation. FIG. 18 is a voltage waveform chart showing a rise of each of the internal power supply voltages VDL1 to VDL4 and VDLP, which is obtained based on the characteristic diagram shown in FIG. 17. Note that FIG. 18 also shows a change of the initialization signal RST from the power-on reset circuit 15.
In FIG. 18, the circuits 11, 14, and 15 receiving the internal power supply voltages VDL1, VDL4, and VDLP, respectively, have a small parasitic capacitance. Accordingly, the levels of the internal power supply voltages VDL1, VDL4, and VDLP rise first. Meanwhile, the circuits 12 and 13 receiving the internal power supply voltages VDL2 and VDL3, respectively, have a large parasitic capacitance. Accordingly, the levels of the internal power supply voltages VDL2 and VDL3 rise with a delay.
In this case, when the internal power supply voltage VDLP supplied to the power-on reset circuit 15 rises up to 0.8 V which is the inversion level (at a time T1), the initialization signal RST from the power-on reset circuit 15 changes from low level to high level. Then, each of the functional circuits 11, 12, 13, and 14 performs the initialization operation in response to the initialization signal RST of high level.
Meanwhile, the internal power supply voltages VDL2 and VDL3 rise only to 0.32 V and 0.53 V, respectively, at the time T1. If the initialization operation is finished when the internal power supply voltages VDL2 and VDL3 are at low level, the initialization operation of each of the command control circuit 12 and the address control circuit 13, which receive the internal power supply voltages VDL2 and VDL3, respectively, is not executed normally. This leads to a problem of causing a malfunction in the operation after power-on.
As a countermeasure for preventing a malfunction from being caused in the initialization operation at power-on, FIG. 4 of Japanese Unexamined Patent Application Publication No. 09-153777, for example, is disclosed as the related art shown in FIG. 19.
In the configuration disclosed in Japanese Unexamined Patent Application Publication No. 09-153777, a first internal voltage generating circuit 18A and a power-on reset circuit 15A are provided to a peripheral circuit 19A, and a second internal voltage generating circuit 18B and a power-on reset circuit 15B are provided to a peripheral circuit 19B.
The power-on reset circuits 15A and 15B are provided to the functional circuits 19A and 19B, respectively, in the above-mentioned manner, and thus the initialization operation is carried out for each of the functional circuits 19A and 19B. Accordingly, all the functional circuits can be normally initialized without the effect of the parasitic capacitance or the like of the functional circuits 19A and 19B.